Typically, memory device is used to store firmware instruction codes that are provided for microprocessors or microcontrollers to execute. When a memory stored with firmware instruction codes is securely mounted on or soldered on an application-specific circuit board or a computer mainboard and is required to be updated, the user tends to perform firmware update operation to the memory without the requirement of removing the memory from its carrier or unsoldering the memory. Therefore, in-circuit programmers are proposed to allow technicians to perform firmware update operations to memory directly in the circuit or system, and have been widely employed.
FIG. 1 is a system block diagram of a conventional in-circuit programming system. As shown in FIG. 1, the in-circuit programming system includes an in-circuit programmer 100 which includes a serial communication interface 160, such as USB interface for receiving firmware instruction codes from a host computer (not shown). The in-circuit programmer 100 further includes a microcontroller 104 for parsing the firmware instruction codes, verifying the content of the firmware instruction codes, and translating the firmware instruction codes into data signals for being programmed into the memory 124. The data signals to be programmed will be transmitted to the output buffer 102 with higher driving capability such that the output buffer 102 can output data signals to a peripheral interface bus 130 when the in-circuit programmer 100 is allowed to program the memory 124. The in-circuit programmer 100 is connected to an application board 120 through a wired peripheral interface bus 130. The application board 120 may be a computer mainboard, and the peripheral interface bus 130 may be a serial (SPI, Microwire etc) or parallel interface bus according to the memory 124 used. The application board 120 includes a bus controller 140 and a memory 124 mounted thereon. The bus controller 140 is configured to access the memory 124 through a system bus 135 in order to fetch the application code and make it run during application life.
FIG. 2 is a system block diagram of a conventional in-circuit programming system for depicting the programming operation when the application board is powered off. It is to be noted that similar circuit elements are labeled with the same reference numerals throughout the entire specification. As shown in FIG. 2, a first RC filter bank 202 is disposed in the in-circuit programmer 100 and connected between the output buffer 102 and an I/O pin 1241 of the memory 124 through node A for removing the noise from the signals outputted from the output buffer 102 and protecting the in-circuit programmer 100 from being short-circuited. Also, a second RC filter bank 204 is disposed in the system bus 135 and connected between the I/O pin 1241 of the memory 124 and an I/O pin 1401 of the bus controller 140 for removing the noise from the signals transmitted on the system bus 135 when the application board 120 is running. As the application board 120 is powered off, the system bus 135 is dedicatedly to be used by the in-circuit programmer 100. Under this condition, the in-circuit programmer 100 must provide an applied voltage Vcc1 to power the memory 124 on the application board 120 for programming. The power provided from the in-circuit programmer 100 is usually isolated from the rest of the application board 120 by using a Diode or MOSFET between the rest components and the memory 124 so that the in-circuit programmer 100 does not supply power to all components of the application board 120. It has to be noted that in order to ensure reliable communication, the high-level output voltages (signals) (Voh) from the in-circuit programmer 100 or from the memory 124 must always be higher than the high-level input voltages (signals) (Vih) of the memory 124 or the in-circuit programmer 100, which is necessary to switch the signal-receiving device to a high state. The voltage level of the high-level output signals (Voh) of the signal-transmitting device will depend on the capability of the buffer (for example the output buffer 102a or the buffer of the memory 124) to drive the output to the power supply level of the signal-receiving device under some current conditions. The voltage level of the high-level input signals (Vih) will depend on the power supply level and input trigger of the signal-receiving device (usually, Vih=Vcc1*0.7V on CMOS compatible device). The output buffer 102a of the in-circuit programmer 100 is configured to provide data signals for being written into the memory 124 with a minimum high-level output voltage of the data signal higher than the high-level output voltage Voh to be decoded by the memory 124 during the memory writing process. The in-circuit programmer 100 further includes an input buffer 102b for receiving data signals from the output of the memory 124 during the memory reading process. The high-level output signals (Voh) of the in-circuit programmer 100 must always be higher than the high-level input signals (Vih) of the memory 124, and the high-level output signals (Voh) of the memory 124 must always been higher than the high-level input signals (Vih) of the in-circuit programmer 100. Electrostatic discharge diodes (ESD diodes) D21 and D22 are designed in the bus controller 140 to protect the input buffer and the output buffer (not shown in FIG. 2) of the bus controller 140 from being damaged by electrostatic charges. When the in-circuit programmer 100 or the memory 124 drives the signals transmitted on the system bus 135 to a high state, a considerable leakage current I1 will be discharged through the bus controller 140, thereby lowering the high-level output voltage Voh. When the application board 120 is powered off and assume that applied voltage Vcc1 supplied by the in-circuit programmer 100 to the output buffer 102a and the memory 124 mounted on the application board 120 is 3.3V, and the resistance of the second RC filter bank 204 between the bus controller 140 and the memory 124 is 33Ω, the high-level input voltage Vih of the memory 124 is Vcc1×0.7=3.3×0.7=2.31V. Therefore, the high-level output voltage Voh of the output buffer 102a of the in-circuit programmer 100 must be higher than 2.31V, thereby making the minimum of the leakage current I1 to be (2.3−0.7)/33=50 mA, where the 0.7V is the turn-on voltage of the ESD diodes D21 and D22. Under this condition, the higher the applied voltage Vcc1 supplied to the internal output buffer 102a and the memory 124 stands, the higher the high-level input voltage Vih of the memory 124 will be. Thus, the high-level output voltage Voh for the in-circuit programmer 100 must increase as well, thereby boosting the leakage current. In the same way, during the reading process, the input buffer 102a of the in-circuit programmer 100 is supplied by Vcc1 and needs a minimum high-level output voltage of signals from the memory 124 higher than the high-level input voltage Vih=3.3X0.7V=2.31V. Because the driving capability of the buffer (not shown) of the memory 124 is typically weak and can not provide a high-level output voltage as high as 2.31V under high current leakage condition, the communication between the in-circuit programmer 100 and the memory 124 would be failed frequently (the high-level output voltage Voh of the memory 124 smaller than the high-level input voltage Vih of the in-circuit programmer 100). Also, the leakage current I1 injecting into the bus controller 140 will damage the bus controller 140, thereby causing inconvenience in circuit design and inflicting perilous danger in use.
FIG. 3 is a system block diagram of a conventional in-circuit programming system for depicting the programming operation when the application board is powered on. As shown in FIG. 3, when the application is powered on, the memory 124 is power-supplied by the application board 120. The in-circuit programmer 100 will issue a reset signal Sr to the bus controller 140 to stop the communication between the bus controller 140 and the memory 124 and fix the I/O pins of the bus controller 140 to a known and stable state. Under the reset state, the I/O pin 1401 of the bus controller 140 will be driven either to a High Impedance (not driven or floating) or Low Impedance (driven Low or driven High) according to the controller design. If the I/O pin 1401 of the bus controller 140 is switched in high impedance, then the in-circuit programmer 100 and the memory 124 can communicate safely without any possible conflict. However, the I/O pin 1401 of the bus controller 140 is more often driven in Low Impedance to reduce consumption or noise. Therefore, the system bus signals of the I/O pin 1401 of the bus controller 140 will be selectively driven High or Low by the bus controller 140. The output buffer 102a of the in-circuit programmer 100 is configured to provide data signals for being written into the memory 124 and a high-level output voltage Voh or low-level output voltage Vol for the memory 124 during the memory writing process. The input buffer 102b is used for receiving data signals from the memory 124 with a high-level input voltage Vih and low-level input voltage Vil requirements during the memory reading process. When the I/O pin of the memory 124 or the in-circuit programmer 100 outputs a high-level output signal Voh at the node A and the I/O pin 1401 of the bus controller 140 outputs a low-level output signal, a large leakage current I1 is induced and flow through the second RC filter bank 204 and injects into the bus controller 140. When the I/O pin of the memory 124 or the in-circuit programmer 100 outputs a low-level output signal at the node A and the I/O pin 1401 of the bus controller 140 outputs a high-level output signal, the leakage current I1 is induced and flow through the second RC filter bank 204 and injects into the in-circuit programmer 100 or the memory 124. Like the example of FIG. 2, the example of FIG. 3 is bound to suffer the deficiencies of FIG. 2 that the buffer of the memory 124 is weak in driving capability to cause communication failure between the in-circuit programmer 100 and the memory 124, and the risk that the leakage current I1 will inject into the bus controller 140 to damage the bus controller 140.
FIG. 4 is a system block diagram of a conventional in-circuit programming system with isolation. In order to prevent the leakage current I1 to be injected into the bus controller 140, an isolation circuit 402 is placed on the system bus 135. The isolation circuit 402 is made up of a MOSFET or switch and is configured to isolate the bus controller 140 from the memory 124 and the in-circuit programmer 100. Also, the isolation circuit 402 is switched to the OPEN state, thereby eliminating leakage current I1. Under this condition, the system bus 135 is driven to a high-impedance state on the memory and programmer side. Although the in-circuit programming system with isolation as shown in FIG. 4 is able to efficiently eliminate the leakage current and ensure a good communication between the in-circuit programmer 100 and memory 124, the manufacturing cost of the application board 120 will greatly increase.
It is required to develop an isolation-free in-circuit programming system that can eliminate the leakage current without an isolation circuit mounted on the application board and lower the requirement of the high-level input voltage of the memory to improve reliability. The invention can address these needs.